1. Field of the Invention
The present invention relates to a phase error detection device, a phase error detecting method, an integrated circuit and an optical disc device each applied to PLL (Phase Locked Loop) for generating a clock brought into phase synchronization with a reproduction signal in order to detect a phase error.
2. Description of the Background Art
As the density of optical discs increases from CDs (Compact Discs) to DVDs (Digital Versatile Discs) and, further to BDs (Blu-ray Discs), such signal processing method as PRML (Partial Response Maximum Likelihood) has become popular. For example, PR (1, 2, 2, 1) ML is employed for a BD with a recording capacity of 25 GB per layer and PR (1, 2, 2, 2, 1) ML is employed for a BD with a recording capacity of 33.3 GB per layer (e.g., refer to “Illustrated Blu-ray Disc Reading Book”, Ohmsha).
In PR (1, 2, 2, 2, 1), as shown in FIG. 25, a signal level continuously takes a value of 0 at a portion where a 2T mark and a 2T space are arranged sequentially. A reliable phase error can not be extracted from a 2T signal portion by a conventional phase error detecting method for detecting a zero-cross point. JP-A-2006-344294 discloses one example in which such a phase error in the 2T signal portion is neglected. In order to exclude the 2T signal portion more accurately, binarization must be performed with good accuracy. Examples of the accurate binarizing method include a convolutional code maximum likelihood decoding method such as a Viterbi decoding method for executing maximum likelihood decoding through use of a repeat structure of a convolutional code.
Incidentally, there is a strong demand for quick recording/reproducing performance along with increase of a recording capacity. In order to make a recording/reproducing time for one disc constant, for example, it is necessary to perform recording/reproducing operations quickly while increasing the recording capacity of the disc.
However, the use of the Viterbi decoding method requires much computing operations. In order to perform the computing operations quickly, pipeline processing must be performed. However, frequent use of pipeline processing causes increase of a delay time during which a phase error is fed back. The increase of such a delay results in a possibility that PLL becomes unstable.
In the conventional phase error detecting method, when a phase error detection range is ±180°, phase inversion occurs repeatedly as a result of detection if a frequency error occurs. Consequently, it takes much time to achieve phase synchronization, and this disadvantage causes a problem that the PLL becomes deteriorated in stability.